- What is the definition of Flip-Flop?
- What are the types of Flip-Flop?
- Why it is called Flip-Flop?
- Why latches cannot be used in combinational circuits?
- Types of triggering:
- What is meant by level triggering?
- What is meant by edge triggering?
- SR Flip-Flop:
- Gated SR Flip-Flop:
- Working of SR Flip-Flop:
- Characteristics Table, Truth Table, Excitation Table of SR Flip-Flop:
- SR Flip-Flop using NAND Gate:
- D Flip-Flop:
- Truth Table, Characteristics Table & Excitation Table of D Flip-Flop:
- JK Flip-Flop:
- Truth Table, Characteristic Table, Excitation Table of JK Flip-Flop:
- T Flip-Flop:
- Truth Table, Characteristics Table& Excitation Table of T Flip-Flop:
- Flip-Flop Characteristics Equation:
- What are the applications of Flip-Flops?
- Some difference between SR Flip-flop & JK Flip-flop:
- Difference between Latches & Flip-Flop:
What is the definition of Flip-Flop?
Flip-flop is a digital circuit that stores a binary bit. In flip-flop the clock signal controls the state of device. It is also called as memory element or a binary storage device.
These circuits have two stable states HIGH & LOW. The circuits remain in one state till the clock signals enables them to change to the other state. This circuits is also called as bi-stable multi vibrator.
A flip-flop’s output is also controlled by its previous and current inputs, but the change in output only happens at precise times set by the clock input.
What are the types of Flip-Flop?
The types of flip-flops are as follows:
- SR Flip-Flop
- D Flip-Flop
- JK Flip-Flop
- T Flip-Flop
Why it is called Flip-Flop?
Flip-flops are bi-stable multi vibrators because they have two stable states. Low (logic 0) and High (logic 1) are the two stable states. The term “flip-flop” is used because these devices can switch between the states when a control signal (such as a clock or enable) is applied, meaning they can “flip” to one state and “flop” back to the other.
Why latches cannot be used in combinational circuits?
Latches uses level variations of the control input to process the input data. This leads to unreliable output. Therefore Edge triggered is used.
Types of triggering:
There are two types of triggering.
- Level Triggering
- Edge Triggering
What is meant by level triggering?
Level triggering occurs when the output changes during either a high voltage or low voltage interval.
What is meant by edge triggering?
The devices which modify their output when signal transitions from a high level to a low level or from a low level to a high level is called edge triggering. Positive and negative edge triggering are two categories for edge triggering.
Positive edge, also known as a rising edge, occurs when the edge transitions from a low state to a high state.
Negative edge, also known as falling edge, occurs when an edge transitions from a high state to a low state.
The SR Flip-flop is a sequential circuit with two inputs: S and R.
- S sets the device (i.e., the output is 1), and
- R resets the device (i.e., the output is 0).
Gated SR Flip-Flop:
SR flip-flop operates with either positive clock transitions or negative clock transitions. The circuit diagram of SR flip-flop can be built using NAND and NOR gate. The operation of SR flip-flop is same as working of SR Latch. The flip-flop operates only with presence of clock transition is Gated SR Flip-flop. Clock pulse is provided in the place of active enable.
Working of SR Flip-Flop:
The invalid state is the issue with S-R flip flops employing NOR and NAND gates. This issue can be solved by using a bi-stable SR flip-flop. This bi-stable SR flip-flop can change outputs when experiencing a specific incorrect state.
This can be done by modifying a standard NOR Gate flip flop into a timed S-R flip flop by include two AND gates. Now the Gated SR Flip flop consists of 3 inputs, ‘S’, ‘R’ & current output Q. The circuit diagram of gated SR Flip-flop is shown below.
The flip-flop operates only when positive clock transition is used in place of active enable. Gated SR flip-flop has three functions:
- Hold State
- Set State
- Reset State
The inputs of the AND Gate receive a clock pulse [CLK]. The outputs of both AND Gates stay “0” when the clock pulse’s value is zero. When a pulse is applied, the value of CLK changes to “1.” As a result, the values at S and R flow via the flip flop of the NOR gate. However, the HIGH value of CLK causes both of them to briefly change to “0” when the values of both S and R values turn “1”. The flip flop state transforms into an intermediate state as soon as the pulse is gone. It depends on whether the set or reset input of the flip-flop retains a “1” longer than the transition to “0” at the end of the pulse for one of the two states to be caused. As a result, the invalid states can be removed.
Characteristics Table, Truth Table, Excitation Table of SR Flip-Flop:
The truth table of SR flip-flop is shown below. The truth table is analyzed with Clock pulse for various inputs and its respective next state output.
Truth table of SR Flip-Flop:
|1||0||0||Qn||No Change (Hold the previous Value)|
Characteristic Table of SR Flip-Flop:
The characteristics table of SR Flip flop is shown below. This table is observed with clock pulse always to be high. The characteristics table provides the information about the upcoming state in response to the specific inputs.
Excitation Table of SR Flip-Flop:
The excitation table of SR flip-flop consists of two columns for the present state (Qn) and the next state (Qn+1) what will be the value of respective inputs S&R.
SR Flip-Flop using NAND Gate:
The D flip-flop is obtained by modifying circuit of clocked SR flip-flop. The complement of the D input is connected to the R input, while the D input is connected to the S input.
When the value of Clock pulse is “1,” the D input is transferred to the flip flop. When clock pulse is high the flip-flop is enabled. The flip flop output is 1 with D= 1 and output is 0 with D = 0. Therefore, D Flip-Flop is said as Delay Flip-Flop or Data Flip-Flop or Transparent Flip-Flop.
The graphical representation, circuit diagram, truth table, characteristics table, excitation table of D Flip Flop is shown below.
Truth Table, Characteristics Table & Excitation Table of D Flip-Flop:
Truth table of D Flip-Flop:
Characteristic Table of D Flip-Flop:
Excitation Table of D Flip-Flop:
A JK Flip-Flop can be defined as modification of SR Flip-Flop. The only difference is the intermediate state is more accurate and refined than that of an S-R flip flop.
Inputs J & K behave in the same way as the S& R inputs of the SR inputs of the SR flip-flop. The letters J and K stand for Set & Clear, respectively.
The flip-flop switches to the complement state when inputs J and K are both in the High State. As a result, when Q=1 it switches to Qn+1= 0, when Q = 0 it switches to Qn+1 = 1.
Two 3-input AND gates are present in the circuit. Along with other inputs like K and the clock pulse [CP], the flip flop’s output Q is fed back to the AND’s input. The flip flop receives a CLEAR signal if the value of CP is “1,” provided that the value of Q was earlier than 1. The output Q’ of the flip flop, together with additional inputs like J and a clock pulse [CP], is similarly provided as feedback to the input of the AND. Thus, only if the value of Q’ was previously 1 does the output become SET when the value of CP is 1.
The graphical representation, circuit diagram, truth table, characteristics table, excitation table of JK Flip Flop is shown below.
Truth Table, Characteristic Table, Excitation Table of JK Flip-Flop:
Truth table of JK Flip-Flop:
Characteristic Table of JK Flip-Flop:
Excitation Table of JK Flip-Flop:
T Flip-flop is simplified form of J-K flip flop. Because the J and K inputs are coupled, the device is often referred to as a single input J-K flip flop. With the clock pulse to be high the input T= 0, output remains in same state. If input T= 1, the output toggles. The graphical representation, circuit diagram, truth table, characteristics table, excitation table of T Flip Flop is shown below.
Truth Table, Characteristics Table& Excitation Table of T Flip-Flop:
Truth table of T Flip-Flop:
Characteristic Table of T Flip-Flop:
Excitation Table of T Flip-Flop:
Flip-Flop Characteristics Equation:
The characteristics equation of JK flip flop is obtained by Karnaugh Map.
SR Flip Flop: Qn+1 = S + QnR’
D Flip Flop: Qn+1 = D
JK Flip Flop: Qn+1 = Q’nJ + QnK’
T Flip Flop: Qn+1 = Q’nT+ QnT’
What are the applications of Flip-Flops?
The applications of flip-flops are:
- Used as the memory & delay element.
- Used for Data transfer.
Some difference between SR Flip-flop & JK Flip-flop:
Indeterminate state does not exist in JK flip flop. Instead of the indeterminate state, the existing state toggles in JK flip flop. In other words, when both inputs are 1, the current state becomes inverted.
Difference between Latches & Flip-Flop:
|Principle||Follow Level triggering||Follows Edge triggering|
|Design||Only designed using Logic gates.||Latches `are used with clock|
|Clock Signal||Operates without Clock||Operates only when clock is present.|
|Sensitivity||Responds only to applied input||Respond to applied input when clock is present|
|Operating Speed||Fast||Slow when compared to Latches|
|Types of operation||Asynchronous circuit||Synchronous circuit|
|Circuit Analysis||Complex||Quite easy|
|Dependent||Operation depends on present, Past input and past output binary values||Operation depends on present, Past input and past output binary values with clock pulse.|
|Types||SR, JK, D & T Latches||SR, JK, D & T Flip-Flop|