PLC

# Implementing SR Flip Flop in PLC Ladder Logic

A key component of sequential logic circuits in digital systems is the SR Flip Flop. Set (S) and Reset (R), its two main inputs, regulate the output’s state.

An SR flip-flop (Set-Reset flip-flop) is a digital memory circuit with two inputs, S (Set) and R (Reset), and two outputs, Q and Q’ (inverse of Q). It operates by setting Q to 1 when S is high, resetting Q to 0 when R is high, and maintaining its state when both inputs are low. Both inputs high create an invalid state, which should be avoided. It’s used in memory storage and control applications.

This article will explain how to utilize PLC ladder logic to create an SR Flip Flop. It will also provide a thorough explanation of the logic diagram and how it relates to PLC ladder logic.

An SR Flip Flop operates based on the combination of the Set and Reset inputs, with the following conditions:

• Set (S) = 1, Reset (R) = 0: The output (Q) is set to 1.
• Set (S) = 0, Reset (R) = 1: The output (Q) is reset to 0.
• Set (S) = 0, Reset (R) = 0: The output (Q) remains in its previous state (no change).
• Set (S) = 1, Reset (R) = 1: This condition is considered invalid or undefined in a standard SR Flip Flop.

SR Flip Flop logic diagram is attached, and it is made up of NAND gates. The output is governed by the input states, which are stated in the previous paragraph. This is an explanation:

• NAND Gate 3: It receives inputs from the Set (S) input and the output of NAND Gate 1. This gate contributes to controlling the Q’ (complement of Q) output.
• NAND Gate 4: It receives inputs from the Reset (R) input and the output of NAND Gate 2. This gate contributes to controlling the Q output.
• NAND Gates 1 and 2: These are cross-coupled with each other, forming the memory function(latching function) of the flip flop, where the output states are held until a change in input occurs.

The attached below PLC ladder diagram demonstrates the implementation of the SR Flip Flop logic:

When the tank level hits a high point in a process plant, a pump must be switched on; alternatively, when it falls to a low point, it must be turned off. The signals from level switches will be used by the SR Flip Flop logic to maintain the pump’s state.

• SET_BIT (%M0): Corresponds to the Set input, activating the output when triggered.
• RESET_BIT (%M1): Corresponds to the Reset input, deactivating the output when triggered.
• HIGH_LEVEL_SWITCH (%I0.0): Represents the Set condition, typically activated by a high-level signal.
• LOW_LEVEL_SWITCH (%I0.1): Represents the Reset condition, typically activated by a low-level signal.
• PUMP_MOTOR_ON (%Q0.0): Represents the Q output, controlling the pump motor state.
• COMPLEMENTARY_NOTUSED (%Q0.1): Represents the Q’ output, which is complementary to the main output and is unused in this example.

Condition:

If the HIGH_LEVEL_SWITCH (I0.0) is activated.

Action:

This sets the SET_BIT (M0), which functions as the “S” (Set) input of the SR Flip-Flop. When this bit is set, it will eventually turn on the pump motor (Q0.0).

Condition:

If the LOW_LEVEL_SWITCH (I0.1) is activated.

Action:

This sets the RESET_BIT (M1), which functions as the “R” (Reset) input of the SR Flip-Flop. When this bit is set, it will turn off the pump motor (Q0.0).

Condition:

The pump motor (Q0.0) will be ON if SET_BIT (M0) is true and RESET_BIT (M1) is false. This mirrors the standard operation of an SR Flip-Flop, where the output is set by the S input and reset by the R input.

Action:

The pump motor (Q0.0) reflects the state of the SR Flip-Flop, being ON when set and OFF when reset. The complementary output (Q0.1) represents the opposite state of Q0.0.

• When the HIGH_LEVEL_SWITCH is activated, it serves as the Set input (S), causing the SR Flip-Flop to set the output (Q0.0) to ON, starting the pump motor.
• When the LOW_LEVEL_SWITCH is activated, it serves as the Reset input (R), causing the SR Flip-Flop to reset the output (Q0.0) to OFF, stopping the pump motor.
• The outputs of this flip-flop are maintained until the respective Set or Reset conditions change.

Condition:

• HIGH_LEVEL_SWITCH (I0.0) is not activated (Set input is absent).
• LOW_LEVEL_SWITCH (I0.1) is not activated (Reset input is absent).

Logic Explanation:

• In the SR Flip-Flop, when both the Set and Reset inputs are inactive (both are “0” or absent), the output maintains its last state. This is a key feature of SR Flip-Flops.
• If the last action was setting the flip-flop (I0.0 was activated previously), the output (Q0.0) will remain ON (keeping the pump motor running) until the reset condition is met.
• If the last action was resetting the flip-flop (I0.1 was activated previously), the output (Q0.0) will remain OFF (keeping the pump motor stopped) until the set condition is met.
• Last State Was Set: If the pump motor was turned ON by the last activation of HIGH_LEVEL_SWITCH (I0.0), and both inputs are now absent, the pump motor will remain ON.
• Last State Was Reset: If the pump motor was turned OFF by the last activation of LOW_LEVEL_SWITCH (I0.1), and both inputs are now absent, the pump motor will remain OFF.

Q0.1 is always the inverse of Q0.0.

• If Q0.0 remains ON (Pump motor ON), Q0.1 will be OFF.
• If Q0.0 remains OFF (Pump motor OFF), Q0.1 will be ON.

The SR Flip-Flop logic guarantees that the output stays in the state it was in even in the absence of activation from either the low-level or high-level switches. Because of this feature, SR Flip-Flops are perfect for controlling processes when it’s important to hold onto the previous state until a fresh new input comes in.